1. Field of the Invention
The present invention relates generally to forming gate dielectric in field effect transistors, and particularly to forming metal oxide/metal silicate gate dielectric films using chemical vapor deposition.
2. Description of the Related Art
The present invention is especially useful in forming complementary metal oxide semiconductor (CMOS) integrated-circuit devices and will be described in that context. Other applications will also be mentioned. CMOS technology has enabled the microelectronic industry to simultaneously meet several technological requirements to fuel market expansion. This has been accomplished largely by a calculated reduction (scaling) of the dimensions of the field-effect transistor (FET). FIG. 1 illustrates portions of a cross sectional view of a field effect transistor (FET) pair in a typical complimentary metal oxide semiconductor (CMOS) device. Device 100 comprises a silicon wafer 155 doped with a p-type material, a p-type epitaxial silicon layer 165 on wafer 155, a p-type well region 120 and an n-type well region 150 defined in epitaxial layer 165, an n-type transistor (NMOS FET) 110 defined in p-well 120 and a p-type transistor (PMOS FET) 140 defined in n-well 150. Region 180 electrically isolates NMOS 110 and PMOS 140 transistors and region 160 electrically isolates the pair of transistors 110 and 140 from other semiconductor devices on substrate 155.
NMOS transistor 110 comprises a gate region 122, a source region 114 and a drain region 116. The source and drain regions are n-type regions on opposite sides of gate region 122. Channel region 118 is interposed between source region 114 and drain region 116. A gate dielectric layer 112 separates channel region 118 and gate region 122. Gate dielectric 112 electrically insulates gate region 122 from channel region 118. The gate region comprises a conductor material, typically doped polycrystalline silicon (polysilicon) or amorphous silicon. The dopant may be an n-type dopant such as a phosphorus or a p-type dopant such as boron. When an appropriate voltage is applied between p-type silicon wafer 155 and gate region 122, electrons from p-well 120 move into region 118 directly below dielectric 112 thereby creating an n-type channel 118. A voltage applied between source 114 and drain 116 causes current to flow between source 114 and drain 116.
PMOS transistor 140 comprises a gate region 152, a source region 144 and a drain region 146. The source and drain regions are p-type regions on opposite sides of gate region 152. Channel region 148 is interposed between source region 144 and drain region 146. A gate dielectric 142 separates channel region 148 and gate region 152. Dielectric 142 electrically insulates gate region 152 from channel region 148. The gate region comprises a conductor material typically doped polysilicon or amorphous silicon. Again, the dopant may be an n-type or p-type material. When an appropriate voltage is applied between p-type silicon wafer 155 and gate region 152, holes from n-well 150 move into region 148 directly below dielectric layer 142 thereby creating a p-type channel 148. A voltage applied between source 144 and drain 146 causes current to flow between source 144 and drain 146.
With the rapid shrinking of the transistor feature size, the gate dielectric thickness has also decreased. For several decades, silicon dioxide has been the material of choice for the gate dielectric layer. Silicon dioxide offers a stable high-quality Si—SiO2 interface and superior electrical isolation properties.
However, as the dimensions of the transistor continue to decrease, the continued use of silicon dioxide as a dielectric gate material is problematic. The fundamental problem is the need to keep the capacitance of the gate high while the area of the gate is shrinking faster than the thickness of the gate dielectric. The capacitance C of the gate is given by C=kE0A/d, wherein A is the area of the gate, d is the thickness of the dielectric layer, k is the dielectric constant, and E0 is the permittivity of free space. In order to ensure higher gate oxide capacitance, the silicon dioxide layer thickness proportionately has been decreased to less than 2 nanometers as the area of the gate has been decreasing. However, future generations will likely require a further reduction to below 1.0 nanometer. The primary issue is that as thickness decreases, leakage current increases. This leakage in current is due primarily to the ability of the electrons to go through the thinner SiO2 dielectric layer. In an example, current density for a 1.5 nanometer thick SiO2 layer at 1 V is 1 A/cm2; however, as the SiO2 thickness decreases to 1 nanometer, the leakage-current density approaches 100 A/cm2 at the same operating voltage.
Consequently, there is a need for an alternative gate dielectric material that can be used in a large enough physical thickness to reduce current leakage density and still provide a high gate capacitance. In order to achieve this, the alternative gate dielectric material must have a dielectric constant that is higher than that of silicon dioxide. Typically, the thickness of such an alternative dielectric material layer is expressed in terms of the equivalent oxide thickness (EOT). Thus, the equivalent oxide thickness (EOT) of an alternative dielectric layer in a particular capacitor is the thickness that the alternative dielectric layer would have if its dielectric constant were that of silicon dioxide.
Another consideration in selecting an alternative dielectric material is the mobility of charge carries in the transistor channel. The material selected for the dielectric film affects the mobility of the carriers in the transistor channel, thereby affecting overall transistor performance. It is desirable to find an alternative dielectric material for which the mobility of carriers in the transistor channel is equivalent to or higher than that for silicon dioxide gate dielectric films. For future generation transistors, a peak mobility of 400 cm2/Vs or greater is desirable.